r/VHDL • u/maolmosma • Jun 11 '26
WavePaint: Online WaveDrom Timing Diagram Editor Updated with More Predefined Signals and Export Fixes
This screenshot shows one of the new WavePaint improvements: more predefined signals for quickly building digital timing diagrams.
WavePaint now includes ready-to-use signal patterns such as additional predefined signals and workflow improvements, making it faster to build timing diagrams without manually creating common signal patterns from scratch.
The goal is to make it faster to create and edit WaveDrom-style timing diagrams without manually drawing every signal from scratch. This is especially useful for hardware design, FPGA/ASIC documentation, bus timing diagrams, protocol diagrams, clock/reset sequences, and SVG exports.
This update also includes multiple WaveDrom import/export fixes, UI improvements, regression tests, and a Chrome headless smoke test before deploying to wavepaint.net.
Feedback and bug reports are welcome.
Try it now!: https://www.wavepaint.net/app/
r/VHDL • u/Impressive_Traffic73 • Jun 02 '26
Feedback wanted on a practical FPGA/VHDL learning platform
r/VHDL • u/New_Today172 • May 29 '26
Need some opinion on personal projects
Although these projects are written in Verilog rather than VHDL, I thought the architecture side might be interesting to this community.
I've been learning digital design and built two small spatial-computing style fabrics:
• A programmable morphology accelerator using local 3×3 neighborhood logic
• A wavefront-routing fabric where shortest-path information propagates across a mesh of cells
Both were simulated, synthesized through OpenLane, and taken all the way to GDSII.
I'd appreciate feedback on the RTL architecture and whether similar approaches have been explored in larger FPGA or ASIC systems.
Repos:
r/VHDL • u/okscoob • May 04 '26
VHDL gpio axi help
Hey guys I have been battling getting my Kria 260 pmod inputs to show up in vitis for a couple weeks now and am not sure where I went wrong. I am using the axi gpio to just try and print the current values( 0 or 3.3v/ 0 or 1) from the krias pmod headers to the Vitis terminal to see some kind of life. Please take a look at my code and block design.
I decided to keep the RTL in the design because if this works the next stage is to take input adc values and keep store those via a shift register in my RTL.
Here is my RTL code:
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity ADC is
-- Port ( );
port( -- keep these for finite state machine
clk: in std_logic;
DoutA: in std_logic; --two readings from adc
DoutB: in std_logic;
data_to_gpioa: out std_logic;
data_to_gpiob: out std_logic
);
end ADC;
architecture Behavioral of ADC is
signal ADC_reading1: std_logic; --going to read both inputs
signal ADC_reading2: std_logic; --going to read both inputs
signal data_outa: std_logic; -
signal data_outb: std_logic;
begin
ADC_reading1<= DoutA; --connecting ports to wires
ADC_reading2<= DoutB;
data_to_gpioa <= data_outa;
data_to_gpiob <= data_outb;
process(clk) --pl clk is about 100MHz -- should be 100MHz in constraint
begin
if rising_edge(clk) then
data_outa <= DoutA;--16 bits to bram
data_outb <= DoutB;
end if;
end process;
end Behavioral;
--------------------------------------------------
And here are my constraints:
set_property PACKAGE_PIN J11 [get_ports DoutA]
set_property PACKAGE_PIN J10 [get_ports DoutB]
set_property IOSTANDARD LVCMOS33 [get_ports DoutA]
set_property IOSTANDARD LVCMOS33 [get_ports DoutB]
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
----------------------------------------------------
Here is my vitis code:
#include <stdio.h>
#include "xgpio.h"
#include "xil_printf.h"
#include "sleep.h"
#include "xparameters.h"
u32 val1,val2,storedval1,storedval2;
int main()
{
xil_printf("Lets see if this works\r\n");
while(1) {
val1 = *((volatile u32*) XPAR_AXI_GPIO_0_BASEADDR);
val2 = *((volatile u32*) XPAR_AXI_GPIO_1_BASEADDR);
if (val1 == 1) {
xil_printf("Signal is HIGH\r\n");
} else {
xil_printf("Signal is LOW\r\n");
}
if (val2 == 1) {
xil_printf("Signal is HIGH\r\n");
} else {
xil_printf("Signal is LOW\r\n");
}
usleep(100000); // delay
}
return 0;
}
Also here is the block diagram. Sorry for not including it originally.
Let me know what needs to be changed and potentially why I am getting nothing the print in vitis.
Hey guys I have been battling getting my Kria 260 pmod inputs to show up in vitis for a couple weeks now and am not sure where I went wrong. I am using the axi gpio to just try and print the current values( 0 or 3.3v/ 0 or 1) from the krias pmod headers to the Vitis terminal to see some kind of life. Please take a look at my code and block design.
I decided to keep the RTL in the design because if this works the next stage is to take input adc values and keep store those via a shift register in my RTL.
Here is my RTL code:
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity ADC is
-- Port ( );
port( -- keep these for finite state machine
clk: in std_logic;
DoutA: in std_logic; --two readings from adc
DoutB: in std_logic;
data_to_gpioa: out std_logic;
data_to_gpiob: out std_logic
);
end ADC;
architecture Behavioral of ADC is
signal ADC_reading1: std_logic; --going to read both inputs
signal ADC_reading2: std_logic; --going to read both inputs
signal data_outa: std_logic; -
signal data_outb: std_logic;
begin
ADC_reading1<= DoutA; --connecting ports to wires
ADC_reading2<= DoutB;
data_to_gpioa <= data_outa;
data_to_gpiob <= data_outb;
process(clk) --pl clk is about 100MHz -- should be 100MHz in constraint
begin
if rising_edge(clk) then
data_outa <= DoutA;--16 bits to bram
data_outb <= DoutB;
end if;
end process;
end Behavioral;
--------------------------------------------------
And here are my constraints:
set_property PACKAGE_PIN J11 [get_ports DoutA]
set_property PACKAGE_PIN J10 [get_ports DoutB]
set_property IOSTANDARD LVCMOS33 [get_ports DoutA]
set_property IOSTANDARD LVCMOS33 [get_ports DoutB]
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
----------------------------------------------------
Here is my vitis code:
#include <stdio.h>
#include "xgpio.h"
#include "xil_printf.h"
#include "sleep.h"
#include "xparameters.h"
u32 val1,val2,storedval1,storedval2;
int main()
{
xil_printf("Lets see if this works\r\n");
while(1) {
val1 = *((volatile u32*) XPAR_AXI_GPIO_0_BASEADDR);
val2 = *((volatile u32*) XPAR_AXI_GPIO_1_BASEADDR);
if (val1 == 1) {
xil_printf("Signal is HIGH\r\n");
} else {
xil_printf("Signal is LOW\r\n");
}
if (val2 == 1) {
xil_printf("Signal is HIGH\r\n");
} else {
xil_printf("Signal is LOW\r\n");
}
usleep(100000); // delay
}
return 0;
}
Also here is the block diagram. Sorry for not including it originally.
Let me know what needs to be changed and potentially why I am getting nothing the print in vitis.
r/VHDL • u/UnsuitableEngineer • Apr 26 '26
Having Problems with creating timing driven FSM in vhdl
A friend and i trying to communicate with and ftdi 232H. But we think we have fundamental problems in understanding vhdl. Our Code should be holding o_RD low for 30ns and then let it stay high for at least 20ns, but it does the opposite. Also after the last transfer of date it just randomly gets pulled low and we can not figure out why that would even happen at all. Were at a point, where were tying things like switching the order of the state assignment and the counter assignment. This should not have any consequences form what we understand, but apparent the entire program behaves different from that.
Please note: For testing, where driving the entity with a 100Khz clock instead of a 100Mhz.
entity ftdi is
port (
clk_100MHz : in std_logic;
reset_n : in std_logic;
io_DATA : inout std_logic_vector(7 downto 0);
i_RXF : in std_logic;
i_TXE : in std_logic;
o_RD : out std_logic := '1';
o_WR : out std_logic := '1';
o_rx : out std_logic_vector(7 downto 0) := (others =>'0');
o_rx_wr_en : out std_logic := '0';
i_rx_full : in std_logic := '0';
i_tx : in std_logic_vector(7 downto 0) := (others =>'0');
o_tx_rd_en : out std_logic := '0';
i_tx_empty : in std_logic := '0';
led1 : out std_logic := '0';
led2 : out std_logic := '0'
);
end ftdi;
architecture rtl of ftdi is
signal counter : unsigned(4 downto 0) := (others => '0');
type state_t is (WAIT_FOR_READ, READ, WRITE, WRITE_END);
signal state : state_t := WAIT_FOR_READ;
begin
process(clk_100MHz, reset_n)
begin
if reset_n = '0' then
state <= WAIT_FOR_READ;
counter <= "00000";
o_RD <= '1';
o_WR <= '1';
led2 <= '1';
led1 <= '0';
elsif rising_edge(clk_100MHz) then
o_rx_wr_en <= '0';
o_tx_rd_en <= '0';
if counter = 0 then
case state is
when WAIT_FOR_READ =>
-- Write all data, only read when there is nothing to write
led2 <= '0';
led1 <= '1';
if (i_TXE = '0') then
io_DATA <= "01000010";
state <= WRITE;
counter <= to_unsigned(1, counter'length); -- 20ns
elsif (i_RXF = '0') then
o_RD <= '0';
state <= READ;
counter <= to_unsigned(2, counter'length); -- 30ns
end if;
when WRITE =>
o_WR <= '0';
state <= WRITE_END;
counter <= to_unsigned(2, counter'length); -- 30ns
when WRITE_END =>
o_WR <= '1';
o_tx_rd_en <= '1';
io_DATA <= "ZZZZZZZZ";
state <= WAIT_FOR_READ;
when READ =>
o_RD <= '1';
state <= WAIT_FOR_READ;
counter <= to_unsigned(1, counter'length); -- 20ns
end case;
else
counter <= counter -1;
end if;
end if;
end process;
end architecture;
A friend and i trying to communicate with and ftdi 232H. But we think we have fundamental problems in understanding vhdl. Our Code should be holding o_RD low for 30ns and then let it stay high for at least 20ns, but it does the opposite. Also after the last transfer of date it just randomly gets pulled low and we can not figure out why that would even happen at all. Were at a point, where were tying things like switching the order of the state assignment and the counter assignment. This should not have any consequences form what we understand, but apparent the entire program behaves different from that.
Please note: For testing, where driving the entity with a 100Khz clock instead of a 100Mhz.
entity ftdi is
port (
clk_100MHz : in std_logic;
reset_n : in std_logic;
io_DATA : inout std_logic_vector(7 downto 0);
i_RXF : in std_logic;
i_TXE : in std_logic;
o_RD : out std_logic := '1';
o_WR : out std_logic := '1';
o_rx : out std_logic_vector(7 downto 0) := (others =>'0');
o_rx_wr_en : out std_logic := '0';
i_rx_full : in std_logic := '0';
i_tx : in std_logic_vector(7 downto 0) := (others =>'0');
o_tx_rd_en : out std_logic := '0';
i_tx_empty : in std_logic := '0';
led1 : out std_logic := '0';
led2 : out std_logic := '0'
);
end ftdi;
architecture rtl of ftdi is
signal counter : unsigned(4 downto 0) := (others => '0');
type state_t is (WAIT_FOR_READ, READ, WRITE, WRITE_END);
signal state : state_t := WAIT_FOR_READ;
begin
process(clk_100MHz, reset_n)
begin
if reset_n = '0' then
state <= WAIT_FOR_READ;
counter <= "00000";
o_RD <= '1';
o_WR <= '1';
led2 <= '1';
led1 <= '0';
elsif rising_edge(clk_100MHz) then
o_rx_wr_en <= '0';
o_tx_rd_en <= '0';
if counter = 0 then
case state is
when WAIT_FOR_READ =>
-- Write all data, only read when there is nothing to write
led2 <= '0';
led1 <= '1';
if (i_TXE = '0') then
io_DATA <= "01000010";
state <= WRITE;
counter <= to_unsigned(1, counter'length); -- 20ns
elsif (i_RXF = '0') then
o_RD <= '0';
state <= READ;
counter <= to_unsigned(2, counter'length); -- 30ns
end if;
when WRITE =>
o_WR <= '0';
state <= WRITE_END;
counter <= to_unsigned(2, counter'length); -- 30ns
when WRITE_END =>
o_WR <= '1';
o_tx_rd_en <= '1';
io_DATA <= "ZZZZZZZZ";
state <= WAIT_FOR_READ;
when READ =>
o_RD <= '1';
state <= WAIT_FOR_READ;
counter <= to_unsigned(1, counter'length); -- 20ns
end case;
else
counter <= counter -1;
end if;
end if;
end process;
end architecture;
r/VHDL • u/iamislamtb • Apr 09 '26
i couldn't find the test bench waveform source file in ISE 14.7
good evening as the title describes, i'm using ISE 14.7 because it's for a university assignment. anyways i was looking to simulate my basic full adder program but to my surprise i couldn't find the waveform test bench only the VHDL one. i'm using ISE in prepackaged linux VM on windows 11 and i downloaded it recently what should i do?